Major automotive chip vendors including NXP are mulling adopting FOPLP (fan-out panel level packaging) technology to process part of their peripheral automotive chips seeking to reduce production costs and meet increasingly robust demand for car-use chips in the next 5-10 years, according to industry sources.

NXP reportedly is in talks with backend partners in Singapore and Malaysia about offering FOPLP services for its automotive chips including MCUs and ECT (engine coolant temperature) sensor chips, the sources said.

The cost of automotive chips packaged with FOPLP technology will be 20% lower than with QFN (quad flat no-lead) process, the sources continued, as long as wafer warpage, yield rate and equipment issues involving the former can be addressed, which, however, still will take some time.

With high stability, heat dissipation and price-performance ratios, QFN wire-bonding process has become the mainstream in recent years for packaging automotive chips, MCUs, power management ICs, driver ICs and other midrange logic ICs, with backend houses ASE and Greatek Electronics and leadframe vendor Chang Wah Technology all sustaining high QFN capacity utilization amid robust demand, the sources said.

Both ASE Technology and Powertech Technology are also keenly proceeding with FOPLP development plans, and will stand a good chance to apply the technology to process automotive chips for international chipmakers or IDMs in the next few years, the sources noted.